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Preliminary Technical Data
FEATURES
Integrated, isolated high-side supply 150mW of secondary side power Isolated high-side and low-side outputs 100mA output source current, 300mA output sink current High common-mode transient immunity: > 25 kV/s High temperature operation: 105C Adjustable Power Level Wide body 16-lead SOIC package Safety and regulatory approvals (pending): UL recognition: 2500 V rms for 1 minute per UL1577
Isolated Half-Bridge Driver with Integrated High-Side Supply ADuM5230
GENERAL DESCRIPTION
The ADuM52301 is an isolated half-bridge gate driver that employs Analog Devices' iCoupler(R) technology to provide independent and isolated high-side and low-side outputs. Combining CMOS and micro-transformer technologies, this isolation component contains an integrated dc-to-dc converter providing an isolated high-side supply. This eliminates the cost, space, and performance difficulties associated with external supply configurations such as a bootstrap circuitry. This highside isolated supply powers not only the ADuM5230 high-side output but also any external buffer circuitry used with the ADuM5230. In comparison to gate drivers employing high voltage level translation methodologies, the ADuM5230 offers the benefit of true, galvanic isolation between the input and each output. Each output can operate up to700 VP relative to the input, thereby supporting low-side switching to negative voltages. The differential voltage between the high-side and low-side may be as high as 700 VP.
1
APPLICATIONS
MOSFET/IGBT gate drive Plasma display modules Motor drives Power Supplies Solar Panel Inverters
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; 7,075,329; and other pending patents.
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
ADuM5230 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Preliminary Technical Data
All voltages are relative to their respective ground. 4.5 V VDD1 5.5 V, 12.0 VDDB 18.0 V. All min/max specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25C, VDD1 = 5.0 V, VDDB = 15 V. Table 1.
Parameter DC SPECIFICATIONS Input Supply Current, Quiescent Channel B Supply Current, Quiescent Channel A Output Supply Voltage At 100 kHz Switching Frequency Maximum Channel A Output Supply Current Input Supply Current Channel B Supply Current At 1000 kHz Switching Frequency Maximum Channel A Output Supply Current Input Supply Current Channel B Supply Current Input Currents Logic High Input Volatge Logic Low Input Voltage Logic High Output Voltages Logic Low Output Voltages Undervoltage Lockout, VISO and VDDB Supply Positive-Going Threshold Negative-Going Threshold Hysteresis Undervoltage Lockout, VDD1 Supply Positive-Going Threshold Negative-Going Threshold Hysteresis Output Short-Circuit Pulsed Current, Sourcing1 Output Short-Circuit Pulsed Current, Sinking1 SWITCHING SPECIFICATIONS Minimum Pulse Width2 Maximum Switching Frequency3 Propagation Delay4 Change vs. Temperature Pulse Width Distortion, |tPLH - tPHL| Channel-to-Channel Matching, Rising or Falling Matching Edge Polarity5 Channel-to-Channel Matching, Rising vs. Falling Opposite Edge Polarity6 Part-to-Part Matching, Rising or Falling Edges7 Part-to-Part Matching, Rising vs. Falling Edges8 Common-Mode Transient Immunity at Logic High Output Common-Mode Transient Immunity at Logic Low Output Symbol IDD1(Q) IDDB(Q) VISO IISO(max, 100) IDD1 IDDB IISO(max, 1000) IDD1 IDDB IIA, IIB VATH, VBTH VATL, VBTL VOAH, VOBH VOAL,VOBL VDDBUV+ VDDBUV- VDDBUVH VDD1UV+ VDD1UV- VDD1UVH IOA, IOB IOA, IOB PW 1000 tPHL, tPLH 100 PWD tM2 tM1 8 8 10 55 63 |CMH| |CML| 25 25 35 35 100 8.0 7.4 0.3 3.5 3.0 0.25 100 300 7.5 200 7.5 +10 0.3 x VDD1 VISO, VDDB 0.1 10.1 9.0 Min Typ Max 125 2 18 Unit mA mA V mA 200 1.8 mA mA mA mA mA A V V V V CL = 200 pF IISO = IISO(max, 100) CL = 200 pF CL = 200 pF IISO = IISO(max, 1000) CL = 200 pF
0 VIA, VIB 5.5V
Test Conditions IISO = 0mA, dc signal inputs, VADJ = Open
12 10
15
-10 0.7 x VDD1 VISO - 0.1, VDDB - 0.1
+0.01
IOA, IOB = -1 mA IOA, IOB = 1 mA
4.2 3.9 mA mA 100 ns kHz ns ps/C ns ns ns ns ns kV/s kV/s CL = 200 pF CL = 200 pF CL = 200 pF CL = 200 pF CL = 200 pF CL = 200 pF CL = 200 pF CL = 200 pF VIx = VDD1, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
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Preliminary Technical Data
Parameter Output Rise Time (10% to 90%) Output Fall Time (10% to 90%)
1 2
ADuM5230
Symbol tR tF Min Typ Max 25 10 Unit ns ns Test Conditions CL = 200 pF, IISO = 13. 5, 100 kHz switching frequency CL = 200 pF, IISO = 13. 5, 100 kHz switching frequency
Short-circuit duration <1 second. Average output current must conform to the limit shown under the Absolute Maximum Ratings. The minimum pulse width is the shortest pulse width at which the specified timing parameters are guaranteed. Operation below the minimum pulse width is strongly discouraged since in some instances pulse stretching to 1uS can occur. 3 The maximum switching frequency is the maximum signal frequency at which the specified timing and power conversion parameters are guaranteed. Operation above the maximum frequency is strongly discouraged. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 "Channel-to-channel matching, rising or falling matching edge polarity" is the magnitude of the propagation delay difference between two channels of the same part when both inputs are either both rising or falling edges. The loads on each channel are equal. 6 "Channel-to-channel matching, rising vs. falling opposite edge polarity" is the magnitude of the propagation delay difference between two channels of the same part when one input is a rising edge and one input is a falling edge. The loads on each channel are equal. 7 Part-to-part matching, rising or falling edges is the magnitude of the propagation delay difference between the same channels of two different parts when the inputs are either both rising or falling edges. The supply voltages, temperatures, and loads of each part are equal. 8 Part-to-part matching, rising vs. falling edges is the magnitude of the propagation delay difference between the same channels of two different parts when one input is a rising edge and the other input is a falling edge. The supply voltages, temperatures, and loads of each part are equal.
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ADuM5230
PACKAGE CHARACTERISTICS
Table 2.
Parameter Resistance (Input-to-Output)1 Capacitance (Input-to-Output)1 Input Capacitance IC Junction-to-Ambient Thermal Resistance
1
Preliminary Technical Data
Symbol RI-O CI-O CI JA
Min
Typ 1012 2.0 4.0 48
Max
Unit pF pF C/W
Test Conditions f = 1 MHz
The device is considered a 2-terminal device: Pin 1 to Pin 8 are shorted together, and Pin 9 to Pin 16 are shorted together.
REGULATORY INFORMATION
The ADuM5230 will be approved by the organization listed in Table 3. Table 3.
UL1 (pending) Recognized under 1577 component recognition program, File E214100
1
In accordance with UL1577, each ADuM5230 is proof-tested by applying an insulation test voltage 3000 V rms for 1 second (current leakage detection limit = 5 A).
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 4.
Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol L(I01) L(I02) Value 2500 8 min 8 min 0.017 min CTI >175 IIIa Unit V rms mm mm mm V Conditions 1 minute duration Measured from input terminals to output terminals, shortest distance through air
Measured from input terminals to output terminals, shortest distance path along body
Distance through the insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1)
RECOMMENDED OPERATING CONDITIONS
Table 5.
Parameter Operating Temperature Input Supply Voltage1 Channel B Supply Voltage1 Input Signal Rise and Fall Times Minimum VDD1 power on slew rate2
1 2
Symbol TA VDD1 VDDB TSLEW
Min -40 4.5 12 400
Max +105 5.5 18 1
Unit C V V ms V/mS
All voltages are relative to their respective ground. The ADuM5230 power supply may fail to properly initialize if VDD1 is applied too slowly
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Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25C, unless otherwise noted. Table 6.
Parameter Storage Temperature (TST) Ambient Operating Temperature (TA) Input Supply Voltage1 (VDD1) Channel B Supply Voltage1 (VDDB) Input Voltage1 (VIA, VIB) Output Voltage1 (VOA, VOB) Input-Output Voltage2 Output Differential Voltage3 Output DC Current (IOA, IOB) Common-Mode Transients4
1 2 3
ADuM5230
Rating -55C to +150C -40C to +105C -0.5 V to +7.0 V -0.5 V to +27 V -0.5 V to VDDI + 0.5 V -0.5 V to VISO + 0.5 V, -0.5 V to VDDB + 0.5 V -700 VPEAK to +700 VPEAK 700 VPEAK -20 mA to +20 mA -100 kV/s to +100 kV/s
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
All voltages are relative to their respective ground. Input-to-output voltage is defined as GNDA - GND1 or GNDB - GND1. Output differential voltage is defined as GNDA - GNDB. 4 Refers to common-mode transients across any insulation barrier. Commonmode transients exceeding the Absolute Maximum Ratings can cause latch-up or permanent damage.
600
500 Safe Operating Vdd1 Current (mA)
400
300
200
100
0 -40
0
40
80
120
160
200
Am bient Tem perature (C)
Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2
Table 7. Maximum Continuous Working Voltage1
Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform Basic Insulation DC Voltage Basic Insulation
1
Max 565 1131 1131
Unit V peak V peak V peak
Constraint 50-year minimum lifetime Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1
Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
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ADuM5230 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
GND1 1 VDD1 2 VADJ 3 GND1 4 VIA 5 VIB 6 VDD1 7 GND1 8 NC = NO CONNECT
16 VOA 15 VISO
Preliminary Technical Data
ADuM5230
TOP VIEW (Not to Scale)
14 GNDISO 13 NC 12 NC 11 GNDB 10 VDDB
07080-002
9
VOB
Figure 3. Pin Configuration
.Table 8. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic GND1 VDD1 VADJ GND1 VIA VIB VDD1 GND1 VOB VDDB GNDB NC NC GNDISO VISO VOA Description Ground Reference for Input Logic Signals. Input Supply Voltage, 4.5 V to 5.5 V. Adjusts Internal DC-to-DC Converter Duty Cycle (Normally Left Unconnected). Ground Reference for Input Logic Signals. Logic Input A. Logic Input B. Input Supply Voltage, 4.5 V to 5.5 V. Ground Reference for Input Logic Signals. Output B Signal. Output B Supply Voltage, 12 V to 18 V. Ground Reference for Output B Signal. No Connect. No Connect. Ground Reference for Output A Signal and Isolated Output Supply Voltage. Isolated Output Supply Voltage. Output A Signal.
Table 9. Truth Table (Positive Logic)
VIA/VIB Input H L X X VDD1 State Powered Powered Unpowered Powered VOA/VOB Output H L L L Notes
Output returns to input state within 1 s of VDDI power restoration.
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Preliminary Technical Data TYPICAL PERFOMANCE CHARACTERISTICS
20 19 18 17 Viso (V) 16 15 14 13 12 11 10 0 5 10 Iiso Load Current (m A) 15 20 4.5V
14
ADuM5230
Viso @ maximum load (V)
5.0V 5.5V
13.5 13
Viso @100kHz Viso @1MHz
12.5
12 11.5
11 -40
0
40
80
120
Temperature (C)
Figure 4. Typical VISO Supply Voltage vs. IISO, external load
Figure 7. Typical VISO output voltage at maximum combined load over temperature
6
200 180 160 Idd1 Current (mA) 140 120 100 80 60 40 20 0 0 5 10 Iiso Load Current (m A) 15 20 4.5V 5.0V 5.5V
0 0 200 400 600 800 1000 1 Vddb (mA) 4 5
3
2
18V 15V 12V
Frequency (kHz)
Figure 5. Typical VDD1 supply Current vs.VISO external load
30 25 20 15 10 5 0 0 5 10 Iiso Load Current (m A) 15 20
Figure 8. Typical VOX output power consumption, CL = 200pF
0 (Voh-Vdd) Output Volatage Drop (V) -0.5 -1 -1.5 -2 -2.5 -3 0 50 100 Ioh (m A) 150 200
Efficiency (%)
4.5V 5.0V 5.5V
Figure 6. Typical VISO supply Efficiency vs. external load Figure 9. Typical VOH vs. IOH(VDD1=5V, VDDB, VISO = 12-18V)
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ADuM5230
2
40.00 35.00
Preliminary Technical Data
Viso=15V Viso=12V
Vol Output Volatage (V)
1.5
Output Current (mA)
30.00 25.00 20.00 15.00 10.00 5.00
1
0.5
0 0 100 200 Iol (m A) 300 400
0.00 0.00 20.00 40.00 60.00 80.00 100.00
PWM Duty Factor (%)
Figure 10. Typical VOL vs. IOL(VDD1=5V, VDDB, VISO = 12-18V) Figure 13. Current Available at the Output vs. PWM Duty Factor for VDD1=5V
70
1
Propagation Delay (nS)
68
0.9 0.8 On Duty Factor
66
0.7 0.6 0.5 0.4 0.3 0.2 0.1 Vdd1=5.0
64
TPlh @ 18V TPhl @ 18V TPlh @ 12V TPhl @ 12V
62
60 -40 0 40 Temperature (C) 80 120
0 0/10 1/9 2/8 3/7 4/6 5/5 6/4 7/3 Upper/Low er Vadj Resistor Values (k )
Figure 11. Typical VISO supply Efficiency vs. load
1600 1400 1200 1000 800 600 400 200 0 1 10 100 1000 Load Impedence ( )
Vdd1=5.5V Vdd1=4.5V
Figure 14. Upper / Lower VADJ Voltage Divider Resistor Values to Determine PWM Duty Factor for VDD1=5V
Power Dissipation (mW)
Figure 12. Power Dissipation vs. Load Impedance for Fault Conditions
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Preliminary Technical Data APPLICATION INFORMATION
THEORY OF OPERATION
The DC/DC converter section of the ADuM5230 works on principles that are common to most modern power supply designs. It is implemented as an open loop PWM controller, which sets the power level being transferred to the secondary. VDD1 power is supplied to an oscillating circuit that switches current into a chip-scale air core transformer. On the secondary side power is rectified to a DC voltage. The voltage is then clamped to approximately 18V and provided to the secondary side VOA data channel and to the VISO pin for external use. The output voltage is unregulated and varies with load. The PWM duty cycle is set by internal bias elements, but can be controlled externally through the VADJ pin with and external resistor network. This feature allows the user to boost the available power at the secondary, or reduce excess power if it is not required for the application. Please refer to the Power Consumption section. Under voltage lockouts are provided on the VDD1, VDDB, and VISO supply lines to interlock the data channels from low supply voltages.
ADuM5230
Figure 15. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the device's Absolute Maximum Ratings, specified in Table 6 leading to latch-up and/or permanent damage. The ADuM5230 is a power device that dissipates about 1W of power when fully loaded and running at maximum speed. Since it is not possible to apply a heat sink to an isolation device, the device primarily depends on heat dissipation into the PCB through the GND pins. If the device will be used at high ambient temperatures, care should be taken to provide a thermal path from the GND pins to the PCB ground plane. The board layout in Figure 15 shows enlarged pads for pins 1 and 8. Multiple vias should be implemented from the pad to the ground plane. This will significantly reduce the temperatures inside of the chip. The dimensions of the expanded pads are left to discretion of the designer and the available board space.
PC BOARD LAYOUT
The ADuM5230 digital isolator with a 150mW isoPower integrated DC/DC converter requires no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins (Figure 15). The power supply section of the ADuM5230 uses a very high oscillator frequency to efficiently pass power through its chip scale transformers. In addition, the normal operation of the data section of the iCoupler introduces switching transients on the power supply pins. Bypass capacitors are required for several operating frequencies. Noise suppression requires a low inductance high frequency capacitor, ripple suppression and proper regulation require a large value capacitor. These are most conveniently connected between Pins 1 and 2 for VDD1 and between Pins 15 and 14 for VISO. To suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. The recommended capacitor values are 0. 1 F, and 10F. It is strongly recommended that a very low inductance ceramic or equivalent capacitor be used for the smaller value. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing with noise suppression and stiffening capacitors is recommended between Pins 1 and 2, a bypass capacitor is recommended between pins 7 and 8. Bypassing with noise suppression and stiffening capacitors is recommended between Pins 14 and 15.
THERMAL ANALYSIS
The ADuM5230 parts consist of several internal die, attached to a three lead frames with three die attach paddles. For the purposes of thermal analysis it is treated as a thermal unit with the highest junction temperature reflected in the JA from Table 2. The value of JA is based on measurements taken with the part mounted on a JEDEC standard 4 layer board with fine width traces and still air. Under normal operating conditions the ADuM5230 will operate at full load across the full temperature range without derating the output current. However, following the recommendations in the PC Board Layout section will decrease the thermal resistance to the PCB allowing increased thermal margin it high ambient temperatures. Under output short circuit conditions as shown in Figure 12, the package power dissipation is within safe operating limits, however, if the load is in the 100ohm range, power dissipation is high enough to cause thermal damage if the ambient temperature is above 80C. Care should be taken to avoid excessive non-short loads if the part is to be operated at high temperatures.
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ADuM5230
100
Preliminary Technical Data
MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss)
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output may differ from the propagation delay to a logic high.
INPUT (VIX) 50%
10
1
0.1
tPLH
OUTPUT (VOX)
tPHL
50%
03786-018
0.01
Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal's timing is preserved. Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM5230 component.
10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 17. Maximum Allowable External Magnetic Flux Density
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than 1 s, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than about 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 9) by the watchdog timer circuit. The limitation on the ADuM5230's magnetic field immunity is set by the condition in which induced voltage in the transformer's receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (-d/dt)rn ; n = 1, 2, ... , N where: is magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuM5230 and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 17.
2
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V--still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM5230 transformers. Figure 18 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM5230 is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted, one would have to place a 0.5 kA current 5 mm away from the ADuM5230 to affect the component's operation.
1000 MAXIMUM ALLOWABLE CURRENT (kA) DISTANCE = 1m 100
10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 18. Maximum Allowable Current for Various Current-to-ADuM5230 Spacings
Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
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03786-020
0.01
03786-019
Figure 16. Propagation Delay Parameters
0.001 1k
Preliminary Technical Data
POWER CONSUMPTION
TRANSIENT IMMUNITY (kV/s) 300
ADuM5230
250 BEST-CASE PROCESS VARIATION 200
The power converter in the ADuM5230 provides 13mA of power to the secondary by default. Output power is shared between the output data channel VOA and VISO for off chip use. The power consumption of VOA varies with frequency and is presented in Figure 8.
150
INCREASING AND DECREASING AVAILABLE POWER
The VADJ pin is used to increase or decrease the available power at the VISO pin. This allows the increase the VISO voltage for a given load or to increase the maximum VISO load. On the other hand, power can also be reduced when it is not required at the output, lowering the quiescent current and saving power. Power adjustment is accomplished by adding a voltage divider between VADJ, VDD1 and GND as shown in Figure 25. Under normal operation, this pin is left open allowing the internal bias network to set the duty factor of the internal PWM. If the VADJ pin is connected via a resistor divider, a duty factor other than the default can be chosen. The relationship between the duty factor of the internal PWM and the available power under load is shown in Figure 13. When the desired duty factor is chosen, the values of the upper and lower divider resistors can be chosen from Figure 14 which assumes a 10k total divider resistance.
100 WORST-CASE PROCESS VARIATION 50
-20
0
20 40 TEMPERATURE (C)
60
80
100
Figure 19. Transient Immunity (Linear Transients) vs. Temperature
The sinusoidal component (at a given frequency) is given by VCM, sinusoidal = V0sin(2ft) where: V0 is the magnitude of the sinusoidal. f is the frequency of the sinusoidal. The transient magnitude of the sinusoidal component is given by dVCM/dt = 2f V0 The ability of the ADuM5230 to operate correctly in the presence of sinusoidal transients is characterized by the data in Figure 20 and Figure 21. The data is based on design simulation and is the maximum sinusoidal transient magnitude (2f V0) that the ADuM5230 can tolerate without an operational error. Values for immunity against sinusoidal transients are not included in Table 5 because measurements to obtain such values have not been possible.
200 180 160 TRANSIENT IMMUNITY (kV/s) 140 120 100 BEST-CASE PROCESS VARIATION 80 60 40 20 WORST-CASE PROCESS VARIATION 0 250 500 750 1000 1250 FREQUENCY (MHz) 1500 1750 2000
07080-004
COMMON-MODE TRANSIENT IMMUNITY
In general, common-mode transients consist of linear and sinusoidal components. The linear component of a commonmode transient is given by VCM, linear = (V/t) t where V/t is the slope of the transient shown in Figure 22 and Figure 23. The transient of the linear component is given by dVCM/dt = V/t The ability of the ADuM5230 to operate correctly in the presence of linear transients is characterized by the data in Figure 19. The data is based on design simulation and is the maximum linear transient magnitude that the ADuM5230 can tolerate without an operational error. This data shows a higher level of robustness than what is shown in Table 5 because the transient immunity values obtained in Table 5 use measured data and apply allowances for measurement error and margin.
0
Figure 20. Transient Immunity (Sinusoidal Transients), 27C Ambient Temperature
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07080-003
0 -40
ADuM5230
200 180 160 TRANSIENT IMMUNITY (kV/s) 140 120 100 80 BEST-CASE PROCESS VARIATION 60 40 20 WORST-CASE PROCESS VARIATION 0 250 500 750 1000 1250 FREQUENCY (MHz) 1500 1750 2000
07080-005
Preliminary Technical Data
voltage transistor combination can be selected to fit the needs of the application.
0
Figure 21. Transient Immunity (Sinusoidal Transients), 100C Ambient Temperature Figure 25.Application Circuit
15V
VDD1 GND1 VDDA AND VDDB
5V
INSULATION LIFETIME
All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation depends on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices conducts an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM5230. Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. Table 7 summarizes the peak voltages for 50 years of service life for a bipolar ac operating condition and the maximum Analog Devices recommended working voltages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. The insulation lifetime of the ADuM5230 depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 26, Figure 27, and Figure 28 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the maximum working voltage recommended by Analog Devices. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 7 can be applied while maintaining the 50-year minimum lifetime provided the voltage
15V
15V VDDA AND VDDB GNDA AND GNDB VDD1 GND1 5V
V t
GNDA AND GNDB
V t
15V
07080-006
Figure 22. Common-Mode Transient Immunity Waveforms--Input to Output
15V
VDDA /VDDB GNDB/GNDB VDDA /VDDB
15V
15V
15V VDDA /VDDB GNDA/GNDB VDDA /VDDB GNDB/GNDB 15V
V t
GNDA/GNDB
V t 15V
07080-007
Figure 23. Common-Mode Transient Immunity Waveforms--Between Outputs
VDDA /VDDB
VDD t VDDA /VDDB GNDA/GNDB GNDA/GNDB
07080-008
Figure 24. Transient Immunity Waveforms--Output Supplies
TYPICAL APPLICATION USAGE
The ADuM5230 is intended for driving low gate capacitance transistors (200 pF typically). Most high voltage applications involve larger transistors than this. To accommodate these application, users can implement a buffer configuration with the ADuM5230, as shown in Figure 25. In many cases, the buffer configuration is the least expensive options and provides the greatest amount of design flexibility. The precise buffer/high
PrF | Page 12 of 14
Preliminary Technical Data
conforms to either the unipolar ac or dc voltage cases. Any cross insulation voltage waveform that does not conform to Figure 27 or Figure 28 should be treated as a bipolar ac waveform and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 7. Note that the voltage presented in Figure 27 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.
RATED PEAK VOLTAGE 0V
ADuM5230
Figure 26. Bipolar AC Waveform
RATED PEAK VOLTAGE
06920-015
0V
Figure 27. Unipolar AC Waveform
RATED PEAK VOLTAGE
06920-016
0V
Figure 28. DC Waveform
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06920-014
ADuM5230 OUTLINE DIMENSIONS
10.50 (0.4134) 10.10 (0.3976)
16 9
Preliminary Technical Data
7.60 (0.2992) 7.40 (0.2913)
1 8
10.65 (0.4193) 10.00 (0.3937)
1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) 0.25 (0.0098)
8 0 0.33 (0.0130) 0.20 (0.0079)
45
SEATING PLANE
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 6. 16-Lead Standard Small Outline Package [SOIC_W]--Wide Body (RW-16) Dimensions shown in millimeters (inches)
ORDERING GUIDE
Model ADUM5230ARWZ2 ADUM5230ARWZ-RL2
1 2
No. of Channels 2 2
Output Peak Current (A)1 0.1/0.3 0.1/0.3
Output Voltage (V) 15 15
032707-B
Temperature Range -40C to +105C -40C to +105C
Package Description 16-Lead SOIC_W 16-Lead SOIC_W, 13-inch Tape and Reel Option (1,000 Units)
Package Option RW-16 RW-16
Sourcing/sinking. Z = RoHS Compliant Part.
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07080-0-3/08(PrF)
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